Ceramic Package in Which Far End Noise is Reduced Using Capacitive Cancellation by Offset Wiring

ABSTRACT

A mechanism for reducing the vertical cross-talk interference experienced in signal lines due to the inductive affects from signal lines in other signal planes of a multi-layer ceramic package is provided. With the apparatus and method, one or more vias in the multi-layer ceramic package may be removed from the structure to provide area through which an offset of the signal lines may pass. Because these offsets of the signal lines exist in parallel planes above or below each other, with no ground lines existing directly between these signal line offsets, a capacitive cross-talk is introduced into the signal lines. This capacitive cross-talk is opposite in polarity to the inductive cross-talk already experienced by the signal lines. As a result, the capacitive cross-talk tends to negate or reduce the inductive cross-talk thereby reducing the far end noise in the signal line.

BACKGROUND OF THE INVENTION

1. Technical Field

The present invention relates generally to an improved apparatus andmethod for noise reduction in multi-layered packages. More specifically,the present invention is directed to an apparatus and method for far endnoise reduction in multi-layered ceramic packages using capacitivecancellation by offset wiring.

2. Description of Related Art

As Very Large Semiconductor Integrated (VLSI) circuits become moredense, there is a need in the art to have semiconductor packagingstructures that can take full advantage of the density and speedprovided by state of the art VLSI devices. Present day modules made ofceramic, typically multilayered ceramic modules, are normally mountedonto cards or boards, with cards or boards combined together to form thecentral processing unit (CPU) of a computer. The multilayer ceramic(MLC) modules typically have VLSI chips mounted on the top surface.

Multilayer modules are used for the packaging of electronic components,especially integrated circuit chips. Both single chip modules (SCM) andmulti chip modules (MCM) are widely used. The most common type of suchmodules is the multilayer ceramic packaging module. In this type ofmodule, the layers consist of a ceramic or glass-ceramic material.However, other types of thick film technologies are known, such as glassepoxy and Teflon. An example of multilayer ceramic packages is providedin U.S. Pat. No. 5,812,380, issued to Frech et al. on Sep. 22, 1998,which is hereby incorporated by reference.

As integrated circuit speeds and packaging densities increase, theimportance of the packaging technology becomes increasingly significant.For example, as devices approach gigahertz speed, inductance effects inthe package become more significant. Such inductance effects may arisefrom switching, for example, and are particularly problematic in powerand ground leads. Inductance effects in the package can cause groundbounce, signal cross-talk and the like. Increasing circuit size andspeed also impact the heat dissipation ability of the package.

VLSI and Ultra Large Semiconductor Integrated (ULSI) chips areespecially designed for high performance applications and are thuslimited by noise. The noise is caused by a high number of simultaneouslyswitching off-chip drivers (OCD noise) and by a high number ofsimultaneously switching latches and the associated logic gates (logicnoise). Both noise sources impact and restrict the on-chip and off-chipperformance and jeopardize the signal integrity. Both noise sourcesgenerate noise due to line-to-line coupling and due to the collapse ofthe voltage-ground (GND) system.

The wiring layers in a typical multi-layer ceramic package are designedin a stacked tri-plate configuration with the signal wiring beingsandwiched between upper and lower reference planes (typicallyalternating in voltage and ground polarity). These reference planes aremeshed in a regular grid structure to allow via interconnections for thesignal and power lines. This tri-plate structure is a controlledimpedance environment that allows high speed signal propagation.

With increased signal rising and falling edge rates and bus signalingspeeds, signals on these wiring layers interact with other signals onthe signal layers above and below it through the meshed referencestructure. This interaction, i.e. cross-talk, between high speed signalsintroduces inter-symbol interference (ISI) on the nets that severelylimits the maximum signaling rates and performance on these nets. ISI isthe distortion of a received signal, wherein the distortion ismanifested in the temporal spreading and consequent overlap ofindividual pulses to the degree that the receiver cannot reliablydistinguish between changes of state, i.e. between individual signalelements. At a certain threshold, inter-symbol interference willcompromise the integrity of the received data.

SUMMARY OF THE INVENTION

In view of the above, it would be beneficial to have an apparatus andmethod that reduces the far end noise in signal lines of a multi-layerceramic package. Moreover, it would be beneficial to have such anapparatus and method that does not increase the cost of the multi-layerceramic package appreciably. Furthermore, it would be beneficial to havesuch an apparatus and method that does not incur any wire channelpenalty.

The present invention provides a mechanism for reducing the verticalcross-talk interference experienced in signal lines due to the inductiveaffects from signal lines in other signal planes of a multi-layerceramic package. With the present invention, one or more vias in themulti-layer ceramic package are removed from the structure to providearea through which an offset of the signal lines may pass. That is,extra signal line length is added to the signal lines such that thesignal line extends into the area where the via would have been, andthen returns to the original path of the signal line in the signalplane.

Because these offsets of the signal lines exist in parallel planes aboveor below each other, with no ground lines existing directly betweenthese signal line offsets, a capacitive cross-talk is introduced intothe signal lines. This capacitive cross-talk is opposite in polarity tothe inductive cross-talk already experienced by the signal lines. As aresult, the capacitive cross-talk tends to negate the inductivecross-talk thereby reducing the far end noise in the signal line.

These and other features and advantages of the present invention will bedescribed in, or will become apparent to those of ordinary skill in theart in view of, the following detailed description of the exemplaryembodiments of the present invention.

BRIEF DESCRIPTION OF THE DRAWINGS

The novel features believed characteristic of the invention are setforth in the appended claims. The invention itself, however, as well asa preferred mode of use, further objectives and advantages thereof, willbest be understood by reference to the following detailed description ofan illustrative embodiment when read in conjunction with theaccompanying drawings, wherein:

FIGS. 1A-1C are exemplary diagrams illustrating a multi-layered ceramicpackage in accordance with a known structure;

FIGS. 2A-2C are figures illustrating the multi-layer ceramic package ofFIGS. 1A-1C in which the top and bottom layers are eliminated;

FIGS. 3A-3C are exemplary diagrams illustrating a multi-layered ceramicpackage in accordance with one exemplary embodiment of the presentinvention;

FIGS. 4A-4C illustrate an exemplary alternative configuration forproviding signal line offsets in accordance with another exemplaryembodiment of the present invention;

FIG. 5 is an exemplary block diagram of a system for generating amulti-layered ceramic package in accordance with one exemplaryembodiment of the present invention; and

FIG. 6 is a flowchart outlining an exemplary operation of the presentinvention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

The present invention provides an improved multi-layered ceramic packageconfiguration in which one or more vias are removed from theconfiguration in order to provide space for additional signal linelength and an area where capacitive cross-talk is introduced tocancel/reduce the magnitude of the far end noise peak. In order toillustrate the primary configuration differences between the improvedmulti-layered ceramic package configuration and known multi-layeredceramic packages, reference will first be made to FIGS. 1A-1C whichillustrate various views of a known multi-layered ceramic package. FIG.1A is an exemplary isometric view diagram illustrating a multi-layeredceramic package in accordance with a known structure. FIG. 1B is anexemplary cross-sectional view of the multi-layered ceramic package inaccordance with a known structure. FIG. 1C is a top view of a ceramicpackage in accordance with a known structure.

As shown in FIGS. 1A-1C, the multi-layered ceramic package 100 includessignal planes 110 (FIG. 1B) sandwiched between reference mesh planes120, 125 and 130. The signal planes 110 are formed as signal wiresformed in a ceramic substrate. The reference mesh planes 120, 125 and130 are ceramic layers with metal wire mesh formed therein. In thedepicted example, the metal wire mesh of the reference mesh planes 120and 130 provide ground (gnd) lines and reference mesh plane 125 providesground (gnd) lines. The vdd lines are accessed by vertical vias 140-146and x-hatch structures with which the vdd vias tie into the vdd meshplane 125. The gnd lines are accessed by ground vias 150-156 and x-hatchstructures with which the gnd vias tie into the ground mesh planes 120and 130. Additional signal planes 110 and mesh planes 120, 125 and 130may be provided in the multi-layered ceramic package 100 as is desiredfor the particular implementation. FIG. 1C illustrates the x-hatchstructures in the reference planes for tying the vdd and gnd vias140-146 and 150-156 to their respective voltage and ground lines in thereference planes 120 and 130.

FIG. 1B illustrates the planes 110-130 in greater detail. As shown inFIG. 1B, the signal planes 110 are separated from one another byreference mesh planes 120, 125 and 130. Because these reference meshplanes 120, 125 and 130 do not exert much influence on the signal planes110, the signal lines 160-169 in the signal planes 110 are inductivelycoupled to one another. This gives rise to noise in the signal lines dueto cross-talk interference. Cross-talk is the undesired, primarilyinductive, interaction between two adjacent metal lines in amulti-layered metallization scheme of an integrated circuit.

As discussed above, as signal rising and falling edge rates and bussignaling speeds increase, signal lines 160-169 on these signal layers110 interact with other signal lines 160-169 on the same signal layer110 and other signal layers 110 above and below it through the referencemesh planes 120, 125 and 130. This cross-talk interaction between highspeed signals introduces noise and inter-symbol interference (ISI) onthe nets that severely limits the maximum signaling rates andperformance on these nets. Thus, in order to be able to achieve highersignaling rates and performance, it is necessary to minimize the noisein signal lines 160-169 of the signal planes 110. Therefore, it isnecessary to have a structure that minimizes the vertical cross-talkinterference experienced by signal lines in one signal plane due tosignal lines in other signal planes.

The present invention provides a mechanism for reducing the verticalcross-talk interference experienced in signal lines due to the inductiveaffects from signal lines in other signal planes of a multi-layerceramic package. With the present invention, one or more vias in themulti-layer ceramic package are removed from the structure to providearea through which an offset of the signal lines may pass. That is,extra signal line length is added to the signal lines such that thesignal line extends into the area where the via would have been, andthen returns to the original path of the signal line in the signalplane.

Because these offsets of the signal lines exist in substantiallyparallel planes above or below each other, with no vdd lines existingdirectly between these signal line offsets, a capacitive cross-talk isintroduced into the signal lines. This capacitive cross-talk is oppositein polarity to the inductive cross-talk already experienced by thesignal lines. As a result, the capacitive cross-talk tends to negate theinductive cross-talk thereby reducing the far end noise in the signalline.

In an alternative embodiment of the present invention, the signal lineoffsets are provided in an area of the signal plane where there are novias present. The signal line offsets are formed such that they extendinto the area and then return to an original signal line path in thesignal plane. This area is aligned with the power/ground mesh planessuch that no ground/power lines are directly between the signal lines ofrespective signal line planes. As a result, capacitive cross-talk isintroduced into the signal lines which reduces the far end noise in thesignal lines. This alternative embodiment has the benefit of not havingto remove a via from the multi-layer ceramic package structure. However,this alternative embodiment can be implemented only in regions that donot have signal vias.

It should also be appreciated that in both embodiments may be combinedsuch that signal line offsets may be formed in areas where there are novias present and in other areas where vias are removed to permit theformation of signal line offsets in accordance with the presentinvention. A signal line offset insertion engine may be provided withlogic for determining where and when to use either approach in a singlemulti-layer ceramic package design, for example.

In order to make the enhancements of the present invention easier toidentify in the figures, the following figures eliminate the top andbottom layers of the tri-plate multi-layer ceramic package shown inFIGS. 1A-1C. It should be appreciated that, while the following figureseliminate these layers from the depictions of the present invention, theactual multi-layer ceramic package produced by the present inventionwill include such layers and that the elimination of these layers isonly for ease of identification of the improvements provided by thepresent invention.

As a basis for comparison, FIGS. 2A-2C are figures illustrating themulti-layer ceramic package of FIGS. 1A-1C in which the top and bottomlayers 120 and 130 are eliminated. The structure shown in FIGS. 2A-2C isidentical to that shown in FIGS. 1A-1C with only the top and bottomlayers 120 and 130, and vias 154 and 156, being removed for ease ofviewing the internal elements of the structure. The elimination of thetop and bottom layers 120 and 130, and vias 154 and 156, in thesefigures is not intended to represent a different structure from thatshown in FIGS. 1A-1C.

FIGS. 3A-3C are exemplary diagrams illustrating a multi-layered ceramicpackage in accordance with one exemplary embodiment of the presentinvention. As with FIGS. 2A-2C above, the top and bottom layer of themulti-layer ceramic package are not shown in FIGS. 2A-2C in order tofacilitate identification of the improvements made by the presentinvention.

As shown in FIGS. 3A-3C, when compared with the similar structure shownin FIGS. 2A-2C, with a first embodiment of the present invention, thevia 150 is removed from the multi-layer ceramic package structure.

While this via 150 may be removed, the x-hatch structures (shown inFIGS. 1A-1C) in the power/ground mesh reference planes 120 and 130 fortying the via 150 to its respective voltage/ground lines in thereference planes 120 and 130 may still be present in the referenceplanes 120 and 130.

In the area of the signal planes 110 through which the via 150 wouldhave passed, signal line offsets 310 and 320 are formed. These signalline offsets extend from the original signal line path to a point Caligned with the center of a grid square in the mesh structure of thereference mesh plane 125. The signal line offsets 310 and 320 thenextend from the center point C back to the original signal line path toform a “U” shaped offset. That is, the signal line offsets 310 and 320depicted in FIGS. 3A-3C are comprised of three approximatelyorthogonally arranged legs: a first leg extending from the originalsignal line path to the center point C of a grid square where the via150 would have been; a second leg extending from the center point C inan approximately orthogonal direction from the first leg to a point inthe signal plane 110 aligned with a ground/power line in the referencemesh plane 125; and a third leg extending approximately orthogonallyfrom the end of the second leg back to the original signal line path.While the offsets 310 and 320 shown in FIGS. 3A-3C are “U” shaped, thepresent invention is not limited to such a configuration and any shapedsignal line offset may be used without departing from the spirit andscope of the present invention.

The first and second legs of the signal line offsets 310 and 320 do nothave any ground/power lines directly between them in the area of thegrid square (the ground/power lines are offset from the signal lines andthus, have less of a shielding influence on the signal lines). As aresult, there is no ground/power line to shield the affects of a signalline on its neighboring signal lines in signal planes both above andbelow it. Thus, the signal line offsets 310 and 320 impose a capacitivecross-talk interference on each other. This capacitive cross-talkinterference, or noise, is opposite in polarity to that of theinductively induced cross-talk already experienced by the signal lines162 and 168. As a result, the capacitive cross-talk noise tends tonegate or reduce the inductively induced cross-talk noise, therebyresulting in a lower far end noise peak.

To illustrate this reduction in cross-talk interference and far endnoise peak, consider the following relationships. For signal lines thatare coupled over a length l, the far end noise increases linearly withcoupled length and is inversely related to rise time (t_(r)). The noisevoltage is given approximately by the equation:V _(FE)=0.5V _(i)(K _(C) −K _(L))(L ₁₁ C ₁₁)^(1/2)(l/t _(r))

where V_(FE) is the far end noise voltage, V_(i) is an input voltage,K_(C) is a capacitive coupling factor, K_(L) is an inductive couplingfactor, L₁₁ is self inductance of line 1 (L₂₂ would be self inductanceof line 2 and L₁₂ would be the mutual inductance between lines 1 and 2),C₁₁ is self capacitance of line 1 (C₂₂ would be self capacitance of line2 and C₁₂ would be the mutual capacitance between lines 1 and 2), t_(r)is the rise time of the signal on the aggressor signal wire. Thecapacitive and inductive coupling factors may be determined asK_(C)=C₁₂/C₁₁ and K_(L)=L₁₂/L₁₁. The result of the above equation isproportional to (K_(c)−K_(L)).

For a positive signal transition (e.g., 0→1 signal transition) on line2, the inductive portion of coupled noise causes a negative pulse (i.e.for a positive transition, or 0 to +Ve voltage change, the noise pulseis a negative transition, or 0 to −Ve transition) on line 1 (V_(L)) andthe capacitive portion of coupled noise causes a positive pulse on line1 (V_(C)). In typical multi-layer ceramic packages, V_(L)>V_(C) inmagnitude. This results in an overall negative (inductive) pulse at thefar end of the signal line. Thus, if the magnitude of V_(C) were to beincreased, the result would be a smaller negative pulse and thus, lessfar end noise.

The present invention achieves such a result by the introduction of thesignal line offsets which introduce a larger capacitive cross-talkbetween two neighboring signal lines in a multi-layer ceramic package.Within the intended operational frequencies of the described structure,the amount of noise that is introduced into the signal lines by way ofthe signal line offsets is primarily a function of the signal edge ratesand not the frequencies of the signals themselves. Thus, the frequenciesof the signals in the described structure do not give rise to problemsassociated with tuned frequencies. At very large signal frequenciesapproach it is possible that problems associated with tuned frequenciesmay become a consideration. However, at this point, it would most likelybe necessary to revise the basic mesh structure of the multi-layerceramic package as well as reconsider the frequency affects of theoffset structure of the present invention.

FIGS. 4A-4C illustrate an exemplary alternative configuration forproviding signal line offsets in accordance with another exemplaryembodiment of the present invention. As shown in FIGS. 4A-4C, thestructure is essentially the same as that shown in FIGS. 3A-3C with theexception that the power/ground via 150 is not removed and the signalline offsets 410 and 420 are provided in a portion of the signal plane110 aligned with a grid square where no via was previously present. Thatis, referring back to FIGS. 2A-2C, the grid square 430 did not have apower/ground or signal via running through the multi-layer ceramicpackage in the area of this grid square 430. Thus, there is no need toremove a via in order to extend the signal wiring into this area.

The signal line offsets 410 and 420 have the same configuration andcharacteristics as the signal line offsets 310 and 320. Thus, in asimilar manner as set forth above with regard to signal line offsets 310and 320, a capacitive cross-talk is introduced by the presence of thesesignal line offsets 310 and 320 in close proximity to each other withouta directly interposed ground/power line between them. Therefore, asimilar result as that obtained from the configuration set forth inFIGS. 3A-3C is obtained. In fact, as will be shown hereafter, a greaterreduction in far end noise is achievable through the use of thisalternative configuration.

Using the above relationships, the following table, Table 1, shows theK_(C), K_(L) and K_(C)+K_(L) values for a glass ceramic multi-layerpackage having the original multi-layer ceramic package configurationillustrated in FIGS. 1A-1C and 2A-2C as well as the configurations shownin FIGS. 3A-3C and 4A-4C: TABLE 1 Coupling Factors for OriginalStructures and Structures of the Present Invention Original Signal LineSignal Line Structure Offset Offset (FIGS. Structure 1 Structure 21A-1C; 2A-2C) (FIGS. 3A-3C) (FIGS. 4A-4C) K_(C) −0.0156 −0.0408 −0.0415K_(L) +0.0385 +0.0530 +0.0502 K_(C) + K_(L) 0.0229 0.0122 0.0087

For each of the signal line offset structures 1 and 2, a glassmulti-layer ceramic package was simulated using 50 ohm source impedance,50 ohm termination impedance, 5 cm long signal lines, and a rise time of100 ps. With this simulation, the following reductions in far end noisein each alternative structure 1 and 2 were observed as a function of howmany times the signal offset structure of the present invention wasimplemented along the length of the signal line: TABLE 2 Reduction in FENoise for Original Structure and Structures of Present Invention %Reduction in FE % Reduction in FE Noise for Noise for Structure 1Structure 2 Original Structure — — (0% of length) Offset implemented−8.5% −8.5% for 8% of total length Offset implemented −14.3% −20.0% for16% of total length Offset implemented −25.7% −37.2% for 33% of totallength

As seen from the above results, by implementing the structures of thepresent invention, depending upon the extent to which the structures arereplicated along the length of the signal line between 0 and 33% of thetotal length, a reduction of approximately 0 to 37.2% in the far endnoise of a signal line may be achievable. Thus, by using the signal lineoffsets of the present invention, a dramatic improvement in the far endnoise of signal lines in a multi-layer ceramic package may be achieved.As a result, the overall affects of cross-talk between high speedsignals and the introduction of inter-symbol interference (ISI) isreduced. This aids in increasing the integrity of the data transmittedalong the nets of the multi-layer ceramic package and thus, increasesthe maximum signaling rates and performance of the multi-layer ceramicpackage.

While the above exemplary embodiments are described as having orthogonalwiring on a glass ceramic module, the present invention is not limitedto such. To the contrary, the present invention may be applied to anymulti-layered ceramic package in which signal line offsets may be formedwith or without the removal of a power/ground via to facilitate thesesignal line offsets. For example, the present invention may beimplemented on 9211 modules, i.e. alumina modules, and with diagonalwiring configurations. Thus, the present invention is equally applicableto any material set that uses signals referenced to meshed planes.

In addition, it should be noted that the techniques for fabricating themulti-layered ceramic package may be any known technique depending uponthe particular materials used. For example, a greensheet technique maybe used to form a multi-layered ceramic package in accordance with thepresent invention. A greensheet technique for a multilayer ceramicpackage fabrication process involves the formation of the green orunfired ceramic layers or sheets, the formation of the conductive paste,the screening of the conductive paste onto the green ceramic sheets andthe stacking, laminating and firing of ceramic sheets into the finalmultilayer ceramic structure. These general processes are known in theart and are described, for example, in U.S. Pat. No. 2,966,719 issued toPark, which is hereby incorporated by reference.

Of course such techniques are modified by introduction of the presentinvention to include signal line offsets in the signal planes of themulti-layered ceramic package at locations where there are no viaspresent or where a power/ground via may be removed to facilitate theintroduction of the signal line offset, as described previously. Otherknown fabrication techniques may be used with the present inventionwithout departing from the spirit and scope of the present invention.

FIG. 5 is an exemplary block diagram of a system for generating amulti-layered ceramic package in accordance with one exemplaryembodiment of the present invention. As shown in FIG. 5, the systemincludes a ceramic package design system 510 coupled to a designanalysis engine 520. Also coupled to the design analysis engine 520 isthe signal line offset insertion engine 530 and a ceramic packagefabrication system 540. The ceramic package design system 510 provides adesign for the multi-layered ceramic package identifying the placementof signal lines, voltage and ground reference mesh layers, voltage andground vias, and the like. The ceramic package design data is providedto the design analysis engine 520 which analyzes the design to identify,among other things, portions of the multi-layer ceramic package wherevias are not present, portions of the multi-layer ceramic package wherepower/ground vias may be removed without significant detrimental affectto the operation of the multi-layer ceramic package, and thus, portionsof the multi-layer ceramic package where signal line offsets may beplaced.

Those vias that may be removed without significant detrimental affectmay be identified, for example, by analyzing the power/ground line andvia portion of the design to identify power/ground vias that are inclose proximity to other power/ground vias that can be used to supplypower/ground connections to surface devices. If a power/ground via is inclose proximity to another power/ground via that can provide thepower/ground connection, then the current power/ground via may beremoved without significant detrimental affect. This is one example foridentifying vias that may be removed, other methods may be used withoutdeparting from the spirit and scope of the present invention.

The identified portions of the multi-layer ceramic package where viasare not present or may be removed are provided to the signal line offsetinsertion engine 530 along with the ceramic package design data. Basedon the identified portions of the multi-layer ceramic package, thesignal line offset insertion engine 530 inserts signal line offsets intothe ceramic package design at the identified locations in the signalplanes where there are either no vias or power/ground vias that may beremoved. The resulting ceramic package design is provided to the ceramicpackage fabrication system 540 for fabrication of the multi-layeredceramic package.

It should be appreciated that the elements shown in FIG. 5 may be partof a system that is implemented as an entirely hardware embodiment, anentirely software embodiment or an embodiment containing both hardwareand software elements. In a preferred embodiment, the elements shown inFIG. 5 are implemented in software, which includes but is not limited tofirmware, resident software, microcode, etc.

Furthermore, the elements of FIG. 5 may take the form of a computerprogram product accessible from a computer-usable or computer-readablemedium providing program code for use by or in connection with acomputer or any instruction execution system. For the purposes of thisdescription, a computer-usable or computer readable medium can be anyapparatus that can contain, store, communicate, propagate, or transportthe program for use by or in connection with the instruction executionsystem, apparatus, or device.

The medium can be an electronic, magnetic, optical, electromagnetic,infrared, or semiconductor system (or apparatus or device) or apropagation medium. Examples of a computer-readable medium include asemiconductor or solid state memory, magnetic tape, a removable computerdiskette, a random access memory (RAM), a read-only memory (ROM), arigid magnetic disk and an optical disk. Current examples of opticaldisks include compact disk-read only memory (CD-ROM), compactdisk-read/write (CD-R/W) and DVD.

A data processing system suitable for storing and/or executing programcode will include at least one processor coupled directly or indirectlyto memory elements through a system bus. The memory elements can includelocal memory employed during actual execution of the program code, bulkstorage, and cache memories which provide temporary storage of at leastsome program code in order to reduce the number of times code must beretrieved from bulk storage during execution.

Input/output or I/O devices (including but not limited to keyboards,displays, pointing devices, etc.) can be coupled to the system eitherdirectly or through intervening I/O controllers.

Network adapters may also be coupled to the system to enable the dataprocessing system to become coupled to other data processing systems orremote printers or storage devices through intervening private or publicnetworks. Modems, cable modem and Ethernet cards are just a few of thecurrently available types of network adapters.

FIG. 6 is a flowchart outlining an exemplary operation of the presentinvention. It will be understood that each block of the flowchartillustration, and combinations of blocks in the flowchart illustration,can be implemented by computer program instructions. These computerprogram instructions may be provided to a processor or otherprogrammable data processing apparatus to produce a machine, such thatthe instructions which execute on the processor or other programmabledata processing apparatus create means for implementing the functionsspecified in the flowchart block or blocks. These computer programinstructions may also be stored in a computer-readable memory or storagemedium that can direct a processor or other programmable data processingapparatus to function in a particular manner, such that the instructionsstored in the computer-readable memory or storage medium produce anarticle of manufacture including instruction means which implement thefunctions specified in the flowchart block or blocks.

Accordingly, blocks of the flowchart illustration support combinationsof means for performing the specified functions, combinations of stepsfor performing the specified functions and program instruction means forperforming the specified functions. It will also be understood that eachblock of the flowchart illustration, and combinations of blocks in theflowchart illustration, can be implemented by special purposehardware-based computer systems which perform the specified functions orsteps, or by combinations of special purpose hardware and computerinstructions.

As shown in FIG. 6, the operation starts by receiving an initialmulti-layered ceramic package design (step 610). The initialmulti-layered ceramic package design is analyzed to identify portions ofmulti-layer ceramic package where vias are either not present orpower/ground vias may be removed without significant detrimental affectto the operation of the multi-layer ceramic package (step 620). Signalline offsets are inserted into the design at the identified portions ofthe multi-layer ceramic package where vias are either not present or maybe removed (step 630). The number of signal line offsets that areinserted along the length of a signal line may be determined based on atable such as that of Table 2 above, depending upon the amount ofreduction in far end noise desired, for example.

The resulting modified multi-layered ceramic package design is thenprovided to a fabrication system (step 640) which fabricates themulti-layered ceramic package based on the modified multi-layeredceramic package design (step 650). The operation then terminates.

Thus, the present invention provides a mechanism through which far endnoise in signal lines of a multi-layer ceramic package may be reduced.The mechanism of the present invention reduces the far end noise byintroducing a capacitive cross-talk into the signal lines that negatesor reduces the inductive cross-talk already experienced by the signallines. The capacitive cross-talk is introduce by way of signal lineoffsets which are capacitively coupled with one another due to the factthat no power/ground line exists directly between these signal lineoffset to shield the capacitive affects of one signal line on the other.

The above embodiments are described in terms of improving the operationof multi-layer ceramic packages that are subject to a ground rule andceramic technology in which it is assumed that K_(C)<K_(L). Namely, thepresent invention increases the capacitive cross-talk so as to decreasethe inductive noise experienced in the signal lines. However, thepresent invention also has applications for other types of technologiesin which such assumptions do not hold. For example, if groundrule/technology of multi-layer ceramic packages is changed to a pointwhere K_(C)>K_(L), i.e. capacitive coupling dominates inductivecoupling, the mechanisms of the present invention may be used to“worsen” K_(L) to compensate for the dominating capacitive coupling.

As described above, in the case were inductive coupling dominatescapacitive coupling, K_(L)>K_(C), the signal line offset is formed in aplane that is substantially parallel to the voltage/ground referencemesh planes. In a case where capacitive coupling dominates inductivecoupling, i.e. K_(C)>K_(L), the signal line offsets may be formed in aplane that is substantially perpendicular to the voltage/groundreference mesh planes. In so doing, the inductive cross-talk isincreased so as to reduce the affects of the capacitive noise, thereby“worsening” K_(L).

The multi-layer ceramic packages as described above may be part of thedesign for an integrated circuit chip. The chip design is created in agraphical computer programming language, and stored in a computerstorage medium (such as a disk, tape, physical hard drive, or virtualhard drive such as in a storage access network). If the designer doesnot fabricate chips or the photolithographic masks used to fabricatechips, the designer transmits the resulting design by physical means(e.g., by providing a copy of the storage medium storing the design) orelectronically (e.g., through the Internet) to such entities, directlyor indirectly. The stored design is then converted into the appropriateformat (e.g., GDSII) for the fabrication of photolithographic masks,which typically include multiple copies of the chip design in questionthat are to be formed on a wafer. The photolithographic masks areutilized to define areas of the wafer (and/or the layers thereon) to beetched or otherwise processed.

The resulting integrated circuit chips can be distributed by thefabricator in raw wafer form (that is, as a single wafer that hasmultiple unpackaged chips), as a bare die, or in a packaged form. In thelatter case the chip is mounted in a single chip package (such as aplastic carrier, with leads that are affixed to a motherboard or otherhigher level carrier) or in a multichip package (such as a ceramiccarrier that has either or both surface interconnections or buriedinterconnections). In any case the chip is then integrated with otherchips, discrete circuit elements, and/or other signal processing devicesas part of either (a) an intermediate product, such as a motherboard, or(b) an end product. The end product can be any product that includesintegrated circuit chips, ranging from toys and other low-endapplications to advanced computer products having a display, a keyboardor other input device, and a central processor.

The description of the present invention has been presented for purposesof illustration and description, and is not intended to be exhaustive orlimited to the invention in the form disclosed. Many modifications andvariations will be apparent to those of ordinary skill in the art. Theembodiment was chosen and described in order to best explain theprinciples of the invention, the practical application, and to enableothers of ordinary skill in the art to understand the invention forvarious embodiments with various modifications as are suited to theparticular use contemplated.

1. A multi-layered ceramic package, comprising: a plurality of signallayers, each signal layer having one or more signal lines; and at leastone reference mesh layer adjacent one or more signal layers of theplurality of signal layers, wherein: the at least one reference meshlayer includes either power lines or ground lines; a first signal linein a first signal layer, and a second signal line in a second signallayer, includes a signal line offset configured such that there is nopower line or ground line directly between the offset in the firstsignal line and the offset in the second signal line; and the signalline offset in the first signal line and the signal line offset in thesecond signal line are capacitively coupled such that capacitivecross-talk is introduced into at least one of the first signal line andthe second signal line to thereby reduce the far end noise in at leastone of the first signal line and the second signal line.
 2. Themulti-layered ceramic package of claim 1, wherein the signal line offsetin the first signal line and the signal line offset in the second signalline are located in portions of the first and second signal layers wherevias are not present.
 3. The multi-layered ceramic package of claim 1,further comprising: at least one via running through one or more signallayers of the plurality of signal layers and one or more reference meshlayers of the at least one reference mesh layer, wherein the signal lineoffset in the first signal layer and the signal line offset in thesecond signal layer are located in portions of the first signal layerand the second signal layer where a via, of the at least one via, hasbeen removed to provide area for the signal line offsets.
 4. Themulti-layered ceramic package of claim 1, wherein the at least onereference mesh layer includes at least two reference mesh layers, andwherein each signal layer of the plurality of signal layers issandwiched between two reference mesh layers of the at least tworeference mesh layers.
 5. The multi-layered ceramic package of claim 1,wherein the signal line offsets are arranged as three approximatelyorthogonally positioned legs extending from an original signal line pathto a position aligned with a center point of a grid square in a meshreference layer, from the center point to an edge of the grid square,and back to the original signal line path.
 6. The multi-layered ceramicpackage of claim 1, wherein the signal line offsets are formed in planesof the plurality of signal layers that are substantially parallel to aplane of the at least one reference mesh layer.
 7. The multi-layeredceramic package of claim 1, wherein the signal line offsets are formedin planes of the plurality of signal layers that are substantiallyperpendicular to a plane of the at least one reference mesh layer. 8-20.(canceled)
 21. The multi-layered ceramic package of claim 1, wherein theplurality of signal layers and the at least one reference mesh layer arefabricated in the multi-layered ceramic package by: receiving an initialmulti-layered ceramic package design; inserting, into the initialmulti-layered ceramic package design, signal line offsets into the firstsignal line of the first signal layer and the second signal line of thesecond signal layer to generate a modified multi-layered ceramic packagedesign; and fabricating the plurality of signal layers and the at leastone reference mesh layer in the multi-layered ceramic package based onthe modified multi-layered ceramic package design.
 22. The multi-layeredceramic package of claim 21, wherein the plurality of signal layers andthe at least one reference mesh layer are further fabricated in themulti-layered ceramic package by: analyzing the initial multi-layeredceramic package design to identify portions of the first signal layerand the second signal layer that do not include vias.
 23. Themulti-layered ceramic package of claim 22, wherein inserting signal lineoffsets into the first signal line and the second signal line includesinserting the signal line offsets at the identified portions of the atleast one reference mesh layer that do not include vias.
 24. Themulti-layered ceramic package of claim 23, wherein the plurality ofsignal layers and the at least one reference mesh layer are furtherfabricated in the multi-layered ceramic package by: analyzing theinitial multi-layered ceramic package design to identify a via that maybe removed to provide area for insertion of signal line offsets;removing the via from the initial multi-layered ceramic package design;and inserting the signal line offsets in the first signal line and thesecond signal line at a portion of the initial multi-layered ceramicpackage design corresponding to the via that has been removed.